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ACPL-312T-000E
Automotive 2.5 Amp Output Current IGBT Gate Drive Optocoupler
Data Sheet
Lead (Pb) Free RoHS 6 fully compliant
RoHS 6 fully compliant options available; -xxxE denotes a lead-free product
Description
The ACPL-312T device contains an AlGaAs LED. The LED is optically coupled to an integrated circuit with a power output stage. This automotive optocoupler is ideally suited for driving power IGBTs and MOSFETs used in automotive motor control inverter and DC-DC converters applications. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by these optocouplers make them ideally suited for directly driving IGBTs with ratings up to 1200 V/100 A. For IGBTs with higher ratings, the ACPL-312T series can be used to drive a discrete power stage which drives the IGBT gate.
Features
* 2.5 A maximum peak output current * 2.0 A minimum peak output current * 25 kV/s minimum Common Mode Rejection (CMR) at VCM = 1500 V * 0.5 V maximum low level output voltage (VOL) Eliminates need for negative gate drive * ICC = 5 mA maximum supply current * Under Voltage Lock-Out protection (UVLO) with hysteresis * Wide operating VCC range: 15 to 30 Volts * 500 ns maximum switching speeds * Automotive temperature range: - -40C to 125C
8 V CC 7 VO 6 VO SHIELD 5 V EE
Functional Diagram
ACPL-312T-000E N/ C 1 ANODE 2 CATHODE 3 N/C 4
* Qualified according to AEC-Q100 Test Guidelines * Safety Approval (Pending): - UL Recognized 3750 Vrms for 1 min. (5kV for option x20E available upon request). - CSA - IEC/EN/DIN EN 60747-5-2
TRUTH TABLE
VCC - VEE "POSITIVE GOING" (i.e., TURN-ON)
0 - 30 V 0 - 11 V 11 - 13.5 V 13.5 - 30 V
Applications
VCC - VEE "NEGATIVE GOING" (i.e., TURN-OFF)
0 - 30 V 0 - 9.5 V 9.5 - 12 V 12 - 30 V
* Automotive Motor/DC-DC Converter * Automotive Isolated IGBT/MOSFET Gate Drive VO LOW LOW TRANSITION HIGH * AC and Brushless DC Motor Drives * Industrial Inverters Systems * Switch mode power supplies
LED OFF ON ON ON
A 0.1 F bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
Options Part Number
ACPL-312T
RoHS Compliant
-000E -300E -500E
Package
DIP 8 Gullwing
Surface Mount
X X
Gullwing
X X
Tape & Reel
UL 5000 Vrms/1 IEC/EN/DIN EN Minute rating 60747-5-2 Quantity
X X 50 per tube 50 per tube 1000 per reel
X
X
Note:- option x20E for UL1577 5000Vrms for 1minute will be offered upon request
To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry.
Example 1:
ACPL-312T-500E to order product of gullwing DIP-8 package in Tape and Reel packaging with RoHS compliant.
Example 2:
ACPL-312T-000E to order product of DIP-8 package in tube packaging with RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Package Outline Drawings
ACPL-312T-000E Standard DIP Package
9.65 0.25 (0.380 0.010) TYPE NUMBER 8 7 312T YYW EE 1 1.19 (0.047) MAX. 2 3 4 1.78 (0.070) MAX. 5 TYP. 3.56 0.13 (0.140 0.005) 4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. 1.080 0.320 (0.043 0.013) 0.65 (0.025) MAX. 2.54 0.25 (0.100 0.010) DIMENSIONS IN MILLIMETERS AND (INCHES). * MARKING CODE LETTER FOR OPTION NUMBERS. "V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 6 5 OPTION CODE* DATE CODE 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010)
LAND PATTERN RECOMMENDATION
2
8
9.65 0.25 (0.380 0.010) 7 6 5
1.016 (0.040)
(0.043 0.013)
2.54 0.25 (0.100 0.010)
OPTION NUMBERS 300 AND 500 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
Gull Wing Surface Mount Option 300
LAND PATTERN RECOMMENDATION 9.65 0.25 (0.380 0.010) 8 7 6 5 6.350 0.25 (0.250 0.010) 3 4 1.27 (0.050) 1.780 (0.070) MAX. 3.56 0.13 (0.140 0.005) 1.080 0.320 (0.043 0.013) 0.635 0.130 2.54 (0.025 0.005) (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. 9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010) 2.0 (0.080) 10.9 (0.430) 1.016 (0.040)
Extended Date Code
1 2
312T YYW EE
1.19 (0.047) MAX.
+ 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002)
0.635 0.25 (0.025 0.010)
12 NOM.
Recommended Pb-Free IR Profile
TIME WITHIN 5 C of ACTUAL PEAK TEMPERATURE Tp 217 C TL TEMPERATURE Tsmax Tsmin 150 - 200 C 260 +0/-5 C RAMP-UP 3 C/SEC. MAX. tp 20-40 SEC.
Regulatory Information
The ACPL-312T-000E is pending approval by the following organizations:
UL
Recognized under UL 1577, component recognition program up to VISO = 3750 VRMS expected prior to product release.
RAMP-DOWN 6 C/SEC. MAX.
CSA
ts PREHEAT 60 to 180 SEC. tL 60 to 150 SEC.
Pending approval under CSA Component Acceptance Notice #5, File CA88324. IEC/EN/DIN EN 60747-5-2
25
t 25 C to PEAK TIME
Approval pending under:
IEC 60747-5-2:1997 + A1:2002 EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884Teil 2):2003-01
Notes: The time from 25 C to peak temperature = 8 minutes max. Tsmax = 200 C, Tsmin = 150 C Non-halide ux should be used
3
Insulation and Safety Related Specifications
Parameter
Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance CTI (Comparative Tracking Index) Isolation Group (DIN VDE0109)
Symbol
L(101) L(102)
Value
7.1 7.4 0.08 >175 IIIa
Units
mm mm mm Volts
Conditions
Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110)
All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics Description
Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 150 V rms for rated mains voltage 300 V rms for rated mains voltage 3450V rms for rated mains voltage 3600V rms for rated mains voltage 1000V rms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b VIORM x 1.875 = VPR, 100% Production Test tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a VIORM x 1.5 = VPR, 100% Type and Sample Test tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage (Transient Overvoltage, tini = 10 sec) Safety Limiting Values (Maximum values allowed in the event of a failure, also see Thermal Derating curve, Figure 11.) Case Temperature Input Current Output Power Insulation Resistance at TS, V10 = 500 V
surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.
Symbol
ACPL-312T
I-IV I-IV I-III
Units
55/125/21 2 VIORM VPR 630 1181 VPEAK VPEAK
VPR
945
VPEAK
VIOTM
6000
VPEAK
Ts Is, INPUT Ps,OUTPUT RIO
175 230 600 109
C mA mW
4
Absolute Maximum Ratings
Parameter
Storage Temperature Operating Temperature Average Input Current Peak Transient Input Current (<1 s pulse width, 300 pps) Reverse Input Voltage "High" Peak Output Current "Low" Peak Output Current Supply Voltage Input Current (Rise/Fall Time) Output Voltage Output Power Dissipation Total Power Dissipation Lead Solder Temperature Solder Reflow Temperature Profile
Symbol
TS TA IF(AVG) IF(TRAN) VR IOH(PEAK) IOL(PEAK) (VCC - VEE) tr(IN) /tf(IN) VO(PEAK) PO PT
Min.
-55 -40
Max.
125 125 20 1.0 5 2.5 2.5
Units
C C mA A V A A Volts ns Volts mW mW
Notes
1
2 2
0 0
35 500 Vcc 370 400
3 4
260C for 10 sec., 1.6 mm below seating plane See Package Outline Drawings Section
Recommended Operating Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage Input Current Input Voltage (OFF)
Symbol
TA (VCC - VEE) IF(ON) VF(OFF)
Min.
-40 15 7 -3.6
Max.
125 30 16 0.8
Units
C Volts mA V
5
DC Electrical Specifications
Over recommended operating conditions (TA = -40 to 125C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.6 to 0.8 V, VCC = 15 to 30 V, VEE = Ground) unless otherwise specified. Parameter
High Level Output Current Low Level Output Current High Level Output Voltage Low Level Output Voltage High Level Supply Current Low Level Supply Current Threshold Input Current Low to High Threshold Input Voltage High to Low Input Forward Voltage Temperature Coefficient of Forward Voltage Input Reverse Breakdown Voltage Input Capacitance UVLO Threshold UVLO Hysteresis
Symbol
IOH IOL VOH VOL ICCH ICCL IFLH VFHL VF VF/TA BVR CIN VUVLO+ VUVLO- UVLOHYS
Min.
0.5 2.0 0.5 2.0
Typ.*
1.5 2.0
Max.
Units
A A A A V
Test Conditions
VO = (VCC - 4 V) VO = (VCC - 15 V) VO = (VEE + 2.5 V) VO = (VEE + 15 V) IO = -100 mA IO = 100 mA Output Open, IF = 7 to 16mA Output Open, VF = -3.0 to +0.8 V IO = 0 mA, VO > 5 V
Fig.
2,3,17
Note
5 2
5,6 ,18 5 2 1,3, 19 6,7 4,6,20 7,8
(VCC - 4) (VCC - 3) 0.1 2.5 2.5 0.8 0.8 1.2 1.5 -1.6 5.0 70 11.0 9.5 12.3 10.7 1.6 13.5 12.0 1.95 0.5 5.0 5.0 5.0
V mA mA mA V V mV/C V pF V V V
9, 15, 21 9
IF = 10 mA IF = 10 mA IR = 10 A f = 1 MHz, VF = 0 V VO > 5 V, IF = 10 mA
16
22, 34
*All typical values at TA = 25C and VCC - VEE = 30 V, unless otherwise noted.
AC Electrical Specifications
Over recommended operating conditions (TA = -40 to 125C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.6 to 0.8 V, VCC = 15 to 30 V, VEE = Ground) unless otherwise specified. Parameter
Propagation Delay Time to High Output Level Propagation Delay Time to Low Output Level Pulse Width Distortion Propagation Delay Difference Between Any Two Parts Rise Time Fall Time UVLO Turn On Delay UVLO Turn Off Delay Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity
Symbol
tPLH tPHL PWD
Min.
0.10 0.10
Typ.*
0.30 0.30
Max.
0.50 0.50 0.3 0.35
Units
s s s s s s s s kV/s kV/s
Test Conditions
Fig.
Note
16
Rg = 10 , Cg = 10 nF, f = 10 10, 11, kHz, Duty Cycle = 50% 12,13, 14, 23
17 35, 36 23 VO > 5 V, IF = 10 mA VO < 5 V, IF = 10 mA TA = 25C, IF = 10 to 16 mA, VCM = 1500 V, VCC = 30 V TA = 25C, VCM = 1500 V, VF = 0 V, VCC = 30 V 24 22 15 13, 14 13, 15 12
PDD -0.35 (tPHL - tPLH) Tr Tf tUVLO ON tUVLO OFF |CMH| |CML| 25 25 0.1 0.1 0.8 0.6 35 35
*All typical values at TA = 25C and VCC - VEE = 30 V, unless otherwise noted.
6
Package Characteristics
Parameter
Input-Output Momentary Withstand Voltage** Resistance (Input-Output) Capacitance (Input-Output) LED-to-Case Thermal Resistance LED-to-Detector Thermal Resistance Detector-to-Case Thermal Resistance
Symbol
VISO RI-O CI-O qLC qLD qDC
Min.
3750
Typ.*
Max.
Units
VRMS
Test Conditions
RH < 50%, t = 1 min. TA = 25C VI-O = 500 VDC = 1 MHz
Fig.
Note
8, 11 11 18
1012 0.8 467 442 126
pF C/W C/W C/W
Thermocouple located at 28 center underside of package
*All typicals at TA = 25C. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refers to your equipment level safety specification or Avago Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage." Notes: 1. Derate linearly above 70C free-air temperature at a rate of 0.0727 mA/C. ' 2. Maximum pulse width = 10 s, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0 A. See Applications section for additional details on limiting IOH peak. 3. Derate linearly above 70C free-air temperature at a rate of 5.0 mW/C. 4. Derate linearly above 70C free-air temperature at a rate of 5.0 mW/C. The maximum LED junction temperature should not exceed 150C. 5. Maximum pulse width = 50 s, maximum duty cycle = 0.5%. 6. In this test VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps. 7. Maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 4500 Vrms for 1 second (leakage detection current limit, II-O 5 A). 8. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 4500 Vrms for 1 second (leakage detection current limit, II-O 5 A). 9. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 6000 Vrms for 1 second (leakage detection current limit, II-O 5 A). 10. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 11. The difference between tPHL and tPLH between any two ACPL-312T parts under the same test condition. 12. Pins 1 and 4 need to be connected to LED common. 13. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15.0 V). 14. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO < 1.0 V). 15. This load condition approximates the gate load of a 1200 V/75A IGBT. 16. Pulse Width Distortion (PWD) is defined as |tPHL-tPLH| for any given device.
7
(VOH - V CC ) - HIGH OUTPUT VOLTAGE DROP - V
0 I OH - OUTPUT HIGH CURRENT - A IF = 7 to 16 mA IOUT = -100 mA V CC = 15 to 30 V V EE = 0 V
2.00 1.95 1.90 1.85 1.80 1.75 1.70 -40 -20 0 20 40 60 80 T A - TEMPERATURE - C 100 120 140 IF = 7 to 16 mA IOUT = -100 mA V CC = 15 to 30 V V EE = 0 V
-1
-2
-3 -40
-20
0
20 40 60 80 T A - TEMPERATURE - C
100
120
140
Figure 1. VOH vs. temperature. 0 -1 -2 -3 -4 -5 -6 IF = 7 to 16 mA V CC = 15 to 30 V V EE = 0 V 0.0 0.5 1.0 1.5 2.0 IOH - OUTPUT HIGH CURRENT - A 2.5 3.0
Figure 2. IOH vs. temperature. 0.25 V OL - OUTPUT LOW VOLTAGE - V 125C -40C 25C 0.20 0.15 0.10 0.05 0.00 V F (OFF) = -3.0 TO 0.8 V IOUT = 100 mA V CC = 15 TO 30 V V EE = 0 V -40 -20 0 20 40 60 80 T A - TEMPERATURE - C 100 120 140
(VOH - V CC ) - OUTPUT HIGH VOLTAGE DROP - V
Figure 3. VOH vs. IOH. 3.00 IOL - OUTPUT LOW CURRENT - A 2.50 2.00 1.50 1.00 0.50 0.00 -40 V F (OFF) = -3.0 TO 0.8 V V OUT = 2.5 V V CC = 15 TO 30 V V EE = 0 V -20 0 20 40 60 80 T A - TEMPERATURE - C 100 120 140
Figure 4. VOL vs. temperature. 4.50 V OL - OUTPUT LOW VOLTAGE - V 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0.0 V F(OFF) = -3.0 to 0.8 V V CC = 15 to 30 V V EE = 0 V 1.0 2.0 3.0 IOL - OUTPUT LOW CURRENT - A 4.0 25C -40C 125C
Figure 5. IOL vs. temperature.
Figure 6. VOL vs. IOL.
8
3.50 ICC - SUPPLY CURRENT - mA ICC - SUPPLY CURRENT - mA Iccl Icch
2.8 2.7 2.6 2.5 2.4 Iccl Icch IF = 10 mA for I CCH IF = 0 mA for I CCL T A = 25 C V EE = 0 V 15 20 25 V CC - SUPPLY VOLTAGE - V 30
3.00
2.50 V CC = 30 V V EE = 0 V IF = 10 mA for I CCH IF = 0 mA for I CCL -40 -20 0 20 40 60 80 T A - TEMPERATURE - C 100 120 140
2.00
1.50
Figure 7. ICC vs. temperature.
Figure 8. ICC vs. VCC.
IFLH - LOW TO HIGH CURRENT THRESHOLD - mA
1.20 T p - PROPAGATION DELAY - ns 1.00 0.80 0.60 0.40 0.20 0.00 -40 -20 0 V CC = 15 TO 30 V V EE = 0 V OUTPUT = OPEN 20 40 60 80 100 T A - TEMPERATURE - C 120 140
500 400
Tplh Tphl
300 200 IF = 10 mA T A = 25 C Rg = 10 Cg = 10 nF DUTY CYCLE = 50% f = 10 kHz 15 20 25 V CC - SUPPLY VOLTAGE - V 30
100
Figure 9. IFLH vs. temperature. 500 Tphl T p - PROPAGATION DELAY - ns 400 300 V CC = 30 V, V EE = 0 V Rg = 10 , Cg = 10 nF T A = 25 C DUTY CYCLE = 50% f = 10 kHz 6 8 10 12 14 IF - FORWARD LED CURRENT - mA 16 500 Tplh
Figure 10. Propagation delay vs. VCC.
500 Tp - PROPAGATION DELAY - ns 400
Tphl Tplh
500
300
200
200 100
IF = 10 mA V CC = 30 V, V EE = 0 V Rg = 10 , Cg = 10 nF DUTY CYCLE = 50% f = 10 kHz -40 -20 0 20 40 60 80 100 T A - TEMPERATURE - C 120 140
100
Figure 11. Propagation delay vs. IF.
Figure 12. Propagation delay vs. temperature.
9
500 T p - PROPAGATION DELAY - ns Tp - PROPAGATION DELAY - ns Tphl 400 300 V CC = 30 V, V EE = 0 V T A = 25 C I F = 10 mA Cg = 10 nF DUTY CYCLE = 50% f = 10 kHz 0 10 20 30 40 Rg - SERIES LOAD RESISTANCE - 50 Tplh
500 Tphl 400 300 V CC = 30 V, V EE = 0 V T A = 25 C IF = 10 mA Cg = 10 nF DUTY CYCLE = 50% f = 10 kHz 0 20 40 60 80 100 Cg - LOAD CAPACITANCE - nF Figure 14. Propagation delay vs. Cg. Tplh
200 100
200 100
Figure 13. Propagation delay vs. Rg.
30 V O - OUTPUT VOLTAGE - V IF - FORWARD CURRENT - mA 25 20 15 10 5 0 0 1 2 3 4 IF - FORWARD LED CURRENT - mA 5
100 o T A = 25 C 10
1
0.1
0.01
1.2
1.3 1.4 1.5 V F - Forward Voltage - VOLTS
1.6
Figure 15. Transfer characteristics.
Figure 16. Input current vs. forward voltage.
10
1 I F = 7 to 16 mA 2 3 4
8 0.1 F 7 6 5 + 4V - + V CC = 15 - to 30 V
1 2 3 4
8 0.1 F 7 6 5
I OL + V CC = 15 - to 30 V 2.5V + -
I OH
Figure 17. IOH test circuit.
Figure 18. IOL Test circuit.
1 I F = 7 to 16 mA 2 3 4
8 0.1 F 7 6
1
VOH + V CC =15 - to 30 V 100 mA
8 0.1 F 7 6 5
2 3 4
100 mA + V CC = 15 - to 30 V VOL
5
Figure 19. VOH Test circuit.
Figure 20. VOL Test circuit.
1 IF 2 3 4
8 0.1 F 7 6 5 VO > 5 V + V CC = 15 - to 30 V
1 I F = 10 mA 2 3 4
8 0.1 F 7 6 5 V O > 5V + V CC -
Figure 21. IFLH Test circuit.
Figure 22. UVLO test circuit.
11
1 I F = 7 to 16 mA + 500 - 2 3 4
8 0.1 F 7 VO 6 5 10 10 nF V CC = 15 + to 30 V -
IF tr tf 90% V OUT t PLH t PHL 50% 10%
10 KHz 50% DUTY CYCLE
Figure 23. tPLH, tPHL, tr, and tf test circuit and waveforms.
V CM IF 5V + - 1 A B 2 3 4 7 6 5 VO + - V CC = 30 V 8 0.1 F 0V t VO SWITCH AT A: I F = 10 mA VO SWITCH AT B: I F = 0 mA
V V CM = t t
V OH
V OL
+ V CM = 1500V
Figure 24. CMR test circuit and waveforms. -
12
Applications Information
Eliminating Negative IGBT Gate Drive ACPL-312T
To keep the IGBT firmly off, the ACPL-312T has a very low maximum VOL specification of 0.5 V. The ACPL-312T realizesthis very low VOL by using a DMOS transistor with 1 (typical) on resistance in its pull down circuit. When the ACPL-312T is in the low state, the IGBT gate is shorted to the emitter by Rg + 1 . Minimizing Rg and the lead inductance from the ACPL-312T to the IGBT gate and emitter (possibly by mounting the ACPL-312T on a small PC board directly above the IGBT) can eliminate the need for nega+5V 270 2 CONTROL INPUT CMOS DRIVER 3 4 ACPL-312T 1 8 0.1 F 7 6 5 Q2
Figure 25. Recommended LED drive and application circuit.
tive IGBT gate drive in many applications as shown in Figure 25. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the ACPL-312T input as this can result in unwanted coupling of transient signals into the ACPL-312T and degrade performance. (If the IGBT drain must be routed near the ACPL-312T input, then the LED should be reverse-biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the ACPL-312T).
+ -
V CC = 18 V Rg Q1
+ HVDC
3-PHASE AC
- HVDC
Selecting the Gate Resistor (Rg) to Minimize IGBT Switching Losses.
Step 1: Calculate Rg Minimum from the IOL Peak Specification. The IGBT and Rg in Figure 26 can be analyzed as a simple RC circuit with a voltage supplied by the HCPL3120. Rg = (VCC -V EE - 2V ) (VCC -V EE -VOL ) = I OLPEAK I OLPEAK R g = 7. 2 8 The VOL value of 2 V in the previous equation is a conservative value of VOL at the peak current of 2.5A (see Figure 6). At lower Rg values the voltage supplied by the ACPL312T is not an ideal voltage step. This results in lower peak currents (more margin) than predicted by this analysis. When negative gate drive is not used VEE in the previous equation is equal to zero volts.
(15 + 5 - 2) 2. 5 A
+5V 270
1 2
8 0.1 F 7 6
+ -
V CC = 15 V Rg
+ HVDC
CONTROL INPUT
CMOS DRIVER
3 4
+ - 5
Q1 V EE = -5 V
3-PHASE AC
Q2
Figure 26. ACPL-312T typical application circuit with negative IGBT gate drive.
- HVDC
13
Step 2: Check the ACPL-312T Power Dissipation and Increase Rg if Necessary.
The ACPL-312T total power dissipation (PT ) is equal to the sum of the emitter power (PE) and the output power (PO): PT PE PO = PE + PO = IF .VF .Duty Cycle = PO(BIAS) + PO (SWITCHING) = ICC.(VCC - VEE) + ESW(RG, QG).f For the circuit in Figure 26 with IF (worst case) = 16 mA, Rg = 8 , Max Duty Cycle = 80%, Qg = 500 nC, f = 20 kHz and TA max = 85C: PE PO = 16 mA.1.8 V.0.8 = 23 mW = 4.25 mA . 20 V + 5.2 J . 20 kHz = 85 mW + 104 mW = 189 mW > 178 mW (PO(MAX) @ 85C = 250 mW-15C*4.8 mW/C) The value of 4.25 mA for ICC in the previous equation was obtained by derating the ICC max of 5 mA (which occurs at -40C) to ICC max at 125C (see Figure 7). Since PO for this case is greater than PO(MAX), Rg must be increased to reduce the ACPL-312T power dissipation. PO(SWITCHING MAX) = PO(MAX) - PO(BIAS) = 178 mW - 85 mW = 93 mW ESW(MAX) = = PO( SWITCHINGMAX) f
P0 Parameter
ICC VCC VEE
Description
Supply Current Positive Supply Voltage Energy Dissipated in the ACPL-312T for each IGBT Switching Cycle (See Figure 27) Switching Frequency
ESW(Rg,Qg) f Esw - ENERGY PER SWITCHING CYCLE - J
14 12 10 8 6 4 2 0 0 10
Qg = 100 nC Qg = 500 nC Qg = 1000 nC V CC = 19 V V EE = -9 V
20 30 40 Rg - GATE RESISTANCE -
50
Figure 27. Energy dissipated in the ACPL-312T for each IGBT switching cycle.
Thermal Model
The steady state thermal model for the ACPL-312T is shown in Figure 28. The thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. As shown by the model, all heat generated flows through qCA which raises the case temperature TC accordingly. The value of qCA depends on the conditions of the board design and is, therefore, determined by the designer. The value of qCA = 83C/W was obtained from thermal measurements using a 2.5 x 2.5 inch PC board, with small traces (no ground plane), a single ACPL-312T soldered into the center of the board and still air. The absolute maximum power dissipation de-rating specifications assume a qCA value of 83C/ W. From the thermal mode in Figure 28 the LED and detector IC junction temperatures can be expressed as:
93mW 20 kHz = 4.65 W
For Qg = 500 nC, from Figure 27, a value of ESW = 4.65 W gives a Rg = 10.3 . PE Parameter
IF VF Duty Cycle
Description
LED Current LED On Voltage Maximum LED Duty Cycle
14
TJE = PE .( LD || DC ) + CA ) + PD .
LC * DC + CA + T A LC + DC + LD
For example, given PE = 30 mW, PO = 230 mW, TA = 100C and qCA = 83C/W: TJE = PE.339C/W + PD.140C/W + TA = 30 mW@339C/W + 230 mW .140C/W + 100C = 142C TJD = PE.140C/W + PD.194C/W + TA = 30 mW.140C/W + 230 mW.194C/W + 100C = 149C TJE and TJD should be limited to 150C based on the board layout and part placement (qCA) specific to the application.
TJD = PE .
LC * DC + CA LC + DC + LD + PD .( DC || LD ) + LC ) +TA
Inserting the values for qLC and qDC shown in Figure 28 gives: TJE TJD = PE.(256C/W + qCA) + PD.(57C/W + qCA) + TA = PE.(57C/W + qCA) + PD.(111C/W + qCA) + TA LD = 442 C/W
T JE T JD TC
T JE T JD TC
LC = 467 C/W
DC = 126 C/W CA = 83 C/W*
TA
LC LD DC CA * CA
= LED junction temperature = detector IC junction temeperature = case temperature measured at the center of the package bottom = LED-to-case thermal resistance = LED-to-detector thermal resistance = detector-to-case thermal resistance = case-to-ambient thermal resistance will depend on the board design and the placement of the part.
Figure 28. Thermal model.
LED Drive Circuit Considerations for Ultra High CMR Performance.
Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 29. The ACPL-312T improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins 5-8 as shown in Figure 30. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 25), can achieve 25 kV/s CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections.
1 1 2 2 3 3 4 4
8 8
1 1 2 2 3 3 4 4
C LEDO1 C LEDO1 C LEDP C LEDP C LEDO2 C LEDO2 C LEDN C LEDN
SHIELD SHIELD
8 8 7 7 6 6 5 5
C LEDP C LEDP
7 7 6 6 5 5
C LEDN C LEDN
Figure 29. Optocoupler input to output capacitance model for unshielded optocouplers.
Figure 30. Optocoupler input to output capacitance model for shielded optocouplers.
15
CMR with the LED On (CMRH).
A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 10 mA provides adequate margin over the maximum IFLH of 5 mA to achieve 25 kV/s CMR. CMR with the LED Off (CMRL). A high CMR LED drive circuit must keep the LED off (VF VF(OFF)) during common mode transients. For example, during a -dVcm/dt transient in Figure 31, the current flowing through CLEDP also flows through the RSAT and VSAT of the logic gate. As long as the low state voltage developed across the logic gate is less than VF(OFF), the LED will remain off and no common mode failure will occur. The open collector drive circuit, shown in Figure 32, cannot keep the LED off during a +dVcm/dt transient, since all the current flowing through CLEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMRL performance. Figure 33 is an alternative drive circuit which, like the recommended application circuit (Figure 25), does achieve ultra high CMR performance by shunting the LED in the off state.
+5V
1 + V SAT - 2 3 4 C LEDP I LEDP C LEDN SHIELD
8 7 6 5 0.1 F + V CC = 18 V -
+5V
1 2 3 4
8
C LEDP
7 6 5
Rg
Q1
C LEDN I LEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING -d VCM /dt. +- V CM Figure 31. Equivalent circuit for figure 25 during common mode transient. Figure 32. Not recommended open collector drive circuit.
+5V
1 2 3 4
8
C LEDP
7 6 5
C LEDN
SHIELD
Figure 33. Recommended LED drive circuit for ultra-high CMR.
16
Under Voltage Lockout Feature.
The ACPL-312T contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the ACPL-312T supply voltage (equivalent to the fully-charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. When the ACPL-312T output is in the high state and the supply voltage drops below the ACPL-312T VUVLO- threshold (9.5 < VUVLO- < 12.0) the optocoupler output will go into the low state with a typical delay, UVLO Turn Off Delay, of 0.6 s. When the ACPL-312T output is in the low state and the supply voltage rises above the ACPL312T VUVLO+ threshold (11.0 < VUVLO+ < 13.5) the optocoupler output will go into the high state (assumes LED is "ON") with a typical delay, UVLO Turn On Delay of 0.8 s.
14 12 V O - OUTPUT VOLTAGE - V 10 8 6 4 2 0 0 (12.3, 0.1) (10.7, 0.1) 5 10 15 (VCC - V EE ) - SUPPLY VOLTAGE - V 20 (10.7, 9.2) (12.3, 10.8)
Dead Time and Propagation Delay Specifications
The ACPL-312T includes a Propagation Delay Difference (PDD) specification intended to help designers minimize "dead time" in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 25) are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worst-case conditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 35. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDDMAX, which is specified to be 350 ns over the operating temperature range of 40C to 125C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specifications as shown in Figure 36. The maximum dead time for the ACPL-312T is 700 ns (= 350 ns - (-350 ns)) over an operating temperature range of -40C to 125C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs.
I LED1
Figure 34. Under voltage lock out. I LED1 VOUT 1 Q1 ON
VOUT 1 Q1 OFF Q2 ON VOUT 2 I LED2
Q1 ON Q2 OFF tPHL MIN tPHL MAX
Q1 OFF Q2 ON
VOUT 2 I LED2
Q2 OFF tPHL MAX
tPLH MIN PDD* MAX = (tPHL- tPLH )MAX =tPHL MAX - tPLH MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure 35. Minimum LED skew for zero dead time.
tPLH
MIN
tPLH MAX (tPHL- tPLH) MAX PDD* MAX MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (tPHL MAX - tPHL MIN) + (tPLH MAX- tPLH MIN) = (tPHL MAX - tPLH MIN ) - (tPHL MIN- tPLH MAX ) = PDD* MAX - PDD* MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure 36. Waveforms for dead time.
17
Output Power Derating Curve
450 400 350 300 Po 250 200 150 100 50 0 0 20 40 60 Ta Figure 37. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN 60747-5-2. 80 100 120 140
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright (c) 2005-2008 Avago Technologies. All rights reserved. AV02-1275EN - July 31, 2008

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